Publications 2025

(Last update: 08/30/2025)

Conferences, Symposiums, and Workshops

  1. Haruki Yoshida, Yuichi Sugiyama, and Ryota Shioya:
    “AceCov: Auxiliary Composite Edge Coverage for Fuzzing”,
    IEEE European Symposium on Security and Privacy (Euro S&P), Venice, Italy, Jun 30 - Jul 4, 2025
  2. Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, and Ryota Shioya:
    “Biotite: A High-Performance Static Binary Translator using Source-Level Information”,
    ACM International Conference on Compiler Construction (CC), March 1–2, 2025, Las Vegas, NV, USA, pp. 167—179.
    DOI: 10.1145/3708493.3712693
    Open Access, Repository
  3. Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, and Hiroki Honda:
    “CACTI-CNFET: An Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors”,
    Asia and South Pacific Design Automation Conference (ASP-DAC), January 20–23, 2025, Tokyo, Japan, pp. 1350—1356.
    DOI: 10.1145/3658617.3697782
  4. Toru Koizumi, Ryota Shioya, Takuya Yamauchi, Tomoya Adachi, Ken Namura, Jun Makino:
    “Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units”,
    IEEE 32nd International Symposium on Computer Arithmetic (ARITH), May 4-7, 2025, El Paso, TX, USA, pp. 21-28.
    DOI: 10.1109/ARITH64983.2025.00014
  5. Toru Koizumi, Toshiki Maekawa, Masanari Mizuno, Maru Kuroki, Tomoaki Tsumura, and Ryota Shioya:
    “RUNLTS: Register-value-aware predictor Utilizing Nested Large TableS”,
    Championship Branch Prediction (CBP2025), in conjunction with ISCA 2025, Jun 21, 2025, Tokyo, Japan, pp. 1—6.
    paper, presentation, code

Journal/Transaction/Letter

  1. Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, and Shuichi Sakai:
    “Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores”,
    IEEE Computer Architecture Letters (CAL) (to appear).

Poster

  1. Chenlin Shi, Toru Koizumi, Ryota Shioya, Hayato Yamaki, Hiroki Honda and Shinobu Miwa:
    “MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Matrix Multiply Operations”
    ACM/IEEE Design Automation Conference (DAC), 2025 (Work-in-Progress Poster Session)